What is IBM's sub-1 nanometer chip technology, and why does it matter?

IBM says it has developed the world's first sub-1 nanometer chip technology. According to Ars Technica, the structure, called nanostack transistors, could boost the performance of chips or allow them to do the same work using less energy.

The basic building block in chips is the transistor. Transistors work like tiny switches that turn an electric current on and off, and a modern processor contains billions of them. For decades the chip industry has made chips faster and more efficient by fitting more transistors into the same area.

The "nanometer" term often heard here once referred to the physical size of transistors. Today these figures have become more like commercial labels naming a generation of manufacturing technology; an expression like "2 nanometer" describes a level of technology rather than a real physical measurement. Even so, the trend is clear: as the number shrinks, denser and more efficient chips are the goal.

The striking part of IBM's announcement is its claim to push this trend below 1 nanometer. The company says it has done this with a new transistor design it calls nanostack. The approach relies on stacking the components of a transistor vertically on top of one another rather than laying them out side by side horizontally.

Vertical stacking aims to get around a fundamental bottleneck in chip design. As transistors shrink horizontally, making them any smaller becomes physically ever harder. Stacking components on top of one another is seen as a way to fit more functionality without increasing the area used — much like building a taller building on a plot rather than spreading out wider.

This design could have two main benefits. The first is boosting performance by fitting more computing power into the same area. The second is achieving the same performance while consuming less energy. Energy efficiency is becoming an increasingly critical issue, particularly in large-scale systems such as data centres and AI workloads.

That said, there is a long road between a laboratory achievement and mass production. New transistor architectures are usually demonstrated first in a research setting; being able to manufacture that structure reliably, at high volume and economically can then take years. IBM's announcement is a research milestone, and when it will appear in products is still uncertain.

In the chip industry, such announcements are read as part of a broader competition. Leading manufacturers are working on different architectural approaches to make transistors smaller and more efficient. Vertical stacking is one of these approaches and offers clues about the industry's future direction.

Experts assess the importance of such advances not in a single device but across the whole ecosystem. More efficient chips can affect the energy footprint of a wide range of devices, from phones to data centres. A step in transistor architecture, while technical on the surface, can therefore touch a broad field of applications.

In the end, IBM's announcement is an example of how the shrinking journey of chips is being taken into new dimensions — this time, quite literally, a vertical one. When and how the technology will translate into products will become clearer over time, but the direction is set: doing more in the same area, with less energy.